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http://en.wikipedia.org/wiki/Northbridge_%28computing%29

Northbrige

The northbridge, also known as the Memory Controller Hub (MCH), is traditionally one of the two chips in the core logic chipset on a PC motherboard, the other being the Southbridge. Separating the chipset into Northbridge and Southbridge is common, although there are rare instances where these two chips have been combined onto one die when design complexity and fabrication processes permit it.

 

The northbridge typically handles communications between the CPU, RAM, AGP or PCI Express, and the southbridge. Some northbridges also contain integrated video controllers, which are also known as a Graphics and Memory Controller Hub (GMCH). Because different processors and RAM require different signalling, a northbridge will typically work with only one or two classes of CPUs and generally only one type of RAM. There are a few chipsets that support two types of RAM (generally these are available when there is a shift to a new standard). For example, the northbridge from the NVIDIA nForce2 chipset will only work with Duron, Athlon, and Athlon XP processors combined with DDR SDRAM, the Intel i875 chipset will only work with systems using Pentium 4 processors or Celeron processors that have a clock speed greater than 1.3 GHz and utilize DDR SDRAM, and the Intel i915g chipset only works with the Intel Pentium 4 and the Intel Celeron, but it can use DDR or DDR2 memory.

 

The name is derived from drawing the architecture in the fashion of a map. The CPU would be at the top of the map at due north. The CPU would be connected to the chipset via a fast bridge (the northbridge) located north of other system devices as drawn. The northbridge would then be connected to the rest of the chipset via a slow bridge (the southbridge) located south of other system devices as drawn.

 

http://en.wikipedia.org/wiki/Southbridge_%28computing%29

Southbridge

, also known as the I/O Controller Hub (ICH), is a chip that implements the "slower" capabilities of the motherboard in a northbridge/southbridge chipset computer architecture. The southbridge can usually be distinguished from the northbridge by not being directly connected to the CPU. Rather, the northbridge ties the southbridge to the CPU.

 

The name is derived from drawing the architecture in the fashion of a map. The CPU would be at the top of the map at due north. The CPU would be connected to the chipset via a fast bridge (the northbridge) located north of other system devices as drawn. The northbridge would then be connected to the rest of the chipset via a slow bridge (the southbridge) located south of other system devices as drawn.

 

Because the southbridge is further removed from the CPU, it is given responsibility for the slower devices on a typical microcomputer. A particular southbridge will usually work with several different northbridges, but these two chips must be designed to work together; there is no industry wide standard for interoperability between different core logic chipset designs. Traditionally this interface between northbridge and southbridge was simply the PCI bus, however since this created a performance bottleneck, most current chipsets use a different (often proprietary) interface with higher performance.

 

The functionality found on a contemporary southbridge includes:

 

    * PCI bus

    * ISA bus

    * SMBus

    * DMA controller

    * Interrupt controller

    * IDE (SATA or PATA) controller

    * LPC Bridge

    * Real Time Clock

    * Power management (APM and ACPI)

    * Nonvolatile BIOS memory

 

Optionally, the southbridge will also include support for Ethernet, RAID, USB, audio codec, and FireWire. Rarely, the southbridge may also include support for the keyboard, mouse, and serial ports, but normally these devices are attached through another device referred to as the Super I/O.

 

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