Toledo døpes Athlon 64 X2?

[Boralis]

Det hadde jeg faktisk regnet med siden Intel har Lansert sin så risikerer de vel ikke å sitte på gjerdet, det har de vel heller ikke råd til.

Men uansett morro at begge kommer med dette omtrent samtidig .

[B-QL]

Mest intresante er dette: "General system availability is scheduled for June, we learned."

 

Kanskje en pre/review i morra?

Endret 20. april 2005 av B-QL

[snorreh]

Nå har også prisene på dobbelkjerne Athlon 64 og andre interessante detaljer lekket ut:

http://www.theinquirer.net/?article=22685

So just what is AMD launching today? Several things, dual core Opterons, dual core Athlon 64s, and Turions for real. Over the past few months, we have told you all about the Opterons, their pricing and the availability, and a few days ago, we told you the same for Athlon 64s. There are a few juicy bits left, and here they are, in no particular order.

 

First up is the Opterons. The 8xx series, 865/870/875 are the ones that AMD is actually going to be shipping today, the 2xx will follow in a month or so. Other than that everything is as we said. They fit in the power envelope of the current chips, and if your board supports 1GHz HT, there is a really good chance your server can take one of these, but it will probably need a BIOS upgrade. The new chips also have the same thermal envelopes as the older single cores.

 

The more interesting introductions are the dual Athlon 64s. There are four models: The 4200+, 4400+, 4600+ and, wait for it, the 4800+. These are 2.2GHz frequency processors with 2x512K cache for $537, and the same with 2x1MB for $581. A 2.4GHz CPU with 2x512 cache will set you back $803, and $1001 for 2x1MB.

Altså blir prisene som følger:

 

Athlon 64 X2 4200+ (2.2GHz, 1MB L2 cache): $537

Athlon 64 X2 4400+ (2.2GHz, 2MB L2 cache): $581

Athlon 64 X2 4600+ (2.4GHz, 1MB L2 cache): $803

Athlon 64 X2 4800+ (2.4GHz, 2MB L2 cache): $1001

Endret 21. april 2005 av snorreh

[Betroz]

Så Athlon 64 X2 4800+ vil koste det samme som Intel sin Extreme Edition prosessor da! Noe som betyr at den vil selge veldig dårlig. Da er Athlon 64 X2 4400+ ett bedre valg. Den kan sikkert overklokkes 200-400 Mhz opp også.

[Malvado]

Så Athlon 64 X2 4800+ vil koste det samme som Intel sin Extreme Edition prosessor da! Noe som betyr at den vil selge veldig dårlig. Da er Athlon 64 X2 4400+ ett bedre valg. Den kan sikkert overklokkes 200-400 Mhz opp også.

Tror nok at det kan være interesant å kjøpe den minste modelen med mest cache, sannsynligvis så kan de fort overklokkes ganske bra, kanskje noen kunnet kjøpt seg en og prøvd seg litt fram snart?

[snorreh]

Anandtech tester Athlon 64 X2 4400+ mot blant annet Pentium 840 EE 3.2GHz her:

http://www.anandtech.com/cpuchipsets/showd...spx?i=2397&p=13

On the desktop side, we are extremely excited about the Athlon 64 X2. The 4400+ we compared here today had no problem competing with and outperforming Intel's fastest dual core CPUs in most cases, and at a price of $581 the 4400+ is the more reasonably priced of the X2 CPUs. That being said, we are concerned that availability of the lower cost X2 CPUs will be significantly more limited than the higher priced models. At the ~550 marker, your best bet is clear - the Athlon 64 X2 will be faster than anything Intel has for the desktop.

Og her er den nye logoen:

 

 

[snorreh]

Legg merke til at Hyperthreading står som enablet.

Mer om dette her: http://www.x86-secret.com/?option=newsd&nid=870

 

So, It seems that AMD chose to activate the "HyperThreading" bit on those  Athlon 64 Desktop CPUs in order to profit from optimizations already done by many programmers for HyperThreading technology.

 

Så var det dette med å svelge kameler

For meg ser det bare ut som om dualcore CPUene er gjort HT kompatible for å utnytte seg av optimaliseringene for HT. En fordel med det er at det kan kjøre Windows XP Pro med to dualcore Opteron fordi den bare registrerer to fysiske kjerner enda det er fire (XP Pro støtter kun to fysiske). Dette er ikke nødvendigvis det samme som HT hvis det kjøres over begge kjernene, bare at den lurer OS til å tro det kun er en fysisk kjerne i stedet for to. Dette burde iallefall stemme hvis alle dualcore CPUene til AMD er gjort HT-kompatible (ikke dermed sagt at det er HT de har).

Hexus skriver mer om dette i sin svært grundige test av Athlon 64 X2 4800+:

http://www.hexus.net/content/reviews/revie...mlld19JRD0xMTcw

Reconciling HyperThreading and SSE3's pair of HT-affecting instructions, would you be surprised to hear that an Athlon 64 X2, one which we know will support SSE3, will also support HTT, too?

 

It does HyperTheading?!

 

Well, sort of. Athlon 64 X2, cheekily leveraging Intel's hard work with Microsoft on Windows XP and Windows 2003's thread scheduler and their push for developers to embrace HyperTheading, advertises itself as supporting HyperThreading when software queries it for available functionality. Execute the right CPUID instruction on an X2 and mask the right place in the bit field for HTT support and you'll see a 1 there, indicating its a HyperThreading processor.

 

For consumer applications that check for the presence of HyperThreading, rather than two physical CPUs, the mechanism for which has existed in Windows operating systems since SMP (symmetric multi-processing) support was added to Windows NT, AMD's dual-core processor should rightfully be able to take advantage of that code and accelerate it.

 

For applications that use the standard ways of the Win32 API, the fact that the X2 is a HyperThreading-compatible CPU is moot, given there is actually more than one physical processor core. They just happen to be on the same silicon wafer and therefore share the same physical package which is placed in just one CPU socket.

 

So regardless of how the app wants to schedule and run a pair of threads, be that normally or with HTT, X2 will let you do so. It's their way of thanking Intel for just copying the x86-64 implementation docs verbatim, to come up with their own x86-64-compatible processors. You use our nice tech, we'll use yours, essentially.

 

And there's more.

 

Compared to Intel's way of doing a dual-core x86 processor, which incidentally apparently doesn't advertise itself as having HTT (unless it's the $1000 Pentium 4 840 Extreme Edition), which will negate a possible performance improvement on applications that only run pairs of threads if the HTT feature flag is exposed, AMD do it a bit differently. And that's all down to the basic architecture they created for Opteron and Athlon 64 during its inception.

[...]

While there's two cores with a Athlon 64 X2 or dual-core Opteron, they share a memory controller on the die. With Intel's dual-core processors, the memory controller is off-die on the northbridge, at the far end of a bus that both cores share to talk to anything external to them. If one core issues a bus request for a memory access, the other has to wait for that to finish before it can do one of its own.

 

Athlon 64 X2 is different in that each core has an individual connection to the memory controller (it's not quite a bus in the CPU sense). If both cores want to access memory, even if that's the same memory location (as long as it's a read request), they can do so at the same time. There's no waiting or bus contention, just regular use of the memory controller as they would if they were singular cores in a non-X2 Athlon 64. The only sticking point lies in the simultaneous update of the same memory location, where arbitration must occur.

[...]

There's also cache coherency to talk about. Back in the days of the Athlon MP, AMD implemented the MOESI cache coherency protocol. MOESI stands for Modify, Owner, Exclusive, Shared, Invalid. Each of those is a state the caches in the system can occupy, depending on what's being done with them by the CPU cores. For example, say that core one updates some memory in its cache, before writing it back out to memory. Core two is always snooping the traffic to core one, and as it spots that happening it marks the caches as Modified, to indicate they're not coherent. In a MESI cache coherency scheme, without the Owner state, if core two wanted to read that memory, it would have to ask core one for it, which tells two to hang on a short while while it writes the data back out to main memory.

 

However, since Athlon MP, single core SMP Opteron and now dual-core Opteron and Athlon 64 X2 have used the Owner state. In the case above, Owner state allows core one to pass the data that core two wanted over the core-to-core interconnect and update the cache on the other CPU directly, without writing it back out to main memory, with the caches then marked as Shared. You can see how that would increase performance.

 

There's less latency when cache data needs to be updated, since you don't need two trips out to main memory, one per core, for a read and write to get the caches back in sync. It's worth noting that Intel's multi-processor Xeon systems currently implement the MESI protocol, so they do have to go out to main memory if cache data is marked Invalid or Modified. I'm not sure how Intel's dual-core processors operate in terms of cache coherency.

 

In a nutshell, if you don't want to wrap your head around cache coherency protocols, the X2 allows the individual caches of each core to be updated without a costly round trip of data into and out of main memory.

 

Cache coherency is one of the main problems to work around when building multi-processor architectures, and only gets harder to do if caches get bigger and you add more processing units to a multi-processor system. It's good to see AMD carry on the work they did with Athlon MP, in that respect.

Meget interessant lesing!

Endret 13. mai 2005 av snorreh