ns på 9600pro

[Thombr86]

hvor står ns'en på rambrikkene på 9600pro fbe, hvilken tall skal jeg se etter?

 

og hvordan reknes teoretisk max mhz ut?

[jcs0607]

tror ns er det siste tallet i en rekke med tall, det som står slik: xxxx-ns

du regner ut max mhz slik: f=1/t

 

f er frekvens

t er periodetid( 1ns er 0.000000001)periodetidener det tallet som står på brikken

[Thombr86]

skjønte ikke så mye av det der :oops:

 

men jeg tar å skriver opp det som står på brikkene:

 

Samsung 223

k4d26323ra-gc2a

 

er det 223 som er ns'en?

[traskas waits for alice]

K4D26323RA

1M x 32Bit x 4 Banks Double Data Rate Synchronous DRAM

 

 

 

 

General Description

 

FOR 1M x 32Bit x 4 Bank DDR SDRAM

The 4Mx32DDR SDRAM is 134,217,728 bits of hyper synchronous data rate Dynamic RAM organized as 4 x1,048,976 words by 32 bits, fabricated with SAMSUNG's high performance CMOS technology. Synchronous features with Data Strobe allow extremely high performance up to 2.8GB/s/chip. I/O transactions are possible on both edges of the clock cycle. Range of operating frequencies, programmable burst length and programmable latencies allow the device to be useful for a variety of high performance memory system applications.

 

 

Features

 

2.8V ± 5% power supply for device operation

2.8V ± 5% power supply for I/O interface

SSTL_2 compatible inputs/outputs

4 banks operation

MRS cycle with address key programs

- Read latency 3,4 (clock)

- Burst length (2, 4, 8 and Full page)

- Burst type (sequential & interleave)

Full page burst length for sequential burst type only

Start address of the full page burst should be even

All inputs except data & DM are sampled at the positive

going edge of the system clock

Differential clock input

No Wrtie-Interrupted by Read Function

4 DQS’s ( 1DQS / Byte )

Data I/O transactions on both edges of Data strobe

DLL aligns DQ and DQS transitions with Clock transition

Edge aligned data & data strobe output

Center aligned data & data strobe input

DM for write masking only

Auto & Self refresh

32ms refresh period (4K cycle)

144-Ball FBGA

Maximum clock frequency up to 350MHz

Maximum data rate up to 700Mbps/pin

 

 

 

 

Dette her hadde du og funnet hadde du søkt litt på google...